CXL Memory Expansion Explained: CXL 2.0 vs 3.0, Type 1/2/3 Devices, and 2026 Sourcing Reality

CXL memory expansion explained, with no marketing varnish: Compute Express Link (CXL) is an open, cache-coherent interconnect built on the PCIe physical layer that allows CPUs to access pooled and disaggregated memory and accelerator resources across a server backplane. Per the CXL Consortium specification, three device classes are defined — Type 1 accelerators with a cache but no host-attached memory; Type 2 accelerators with directly attached memory under host coherence; and Type 3 memory expanders that present DRAM or persistent memory to the CPU over CXL.mem. CXL 2.0 (2020) introduced switching, hot-plug, and memory pooling; CXL 3.0 (2022) added fabric-level memory sharing, multi-level switching, and 64 GT/s signalling on the PCIe 6.0 PAM4 physical layer; CXL 3.1 (2023) refined fabric manageability without changing the wire speed. For any engineering team trying to plan a 2026 AI-server or in-memory-database refresh, those three Type classes and three spec revisions are the only structure that matters.

We get the same call from system architects roughly twice a month. It usually starts with: “Our Sapphire Rapids or Granite Rapids platform supports CXL 2.0 — can you quote us a Micron CZ120 256 GB module?” The honest answer is uncomfortable, and it is the reason this guide exists: the parts are real, the silicon is real, the OEM data sheets are real, and almost none of it is buyable on the open market in 2026 in any volume that resembles “stock”. This article is the reference we send those teams before the second meeting.

Why CXL exists: the memory-bandwidth wall behind AI servers

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DDR5 RDIMM bandwidth scales with channel count, not capacity. A two-socket Granite Rapids host caps out at twelve channels per socket, and once those slots are full, adding more capacity means a bigger DIMM at the same channel count — capacity grows, bandwidth-per-gigabyte falls. For inference workloads with large embedding tables, Spark in-memory analytics, or SAP HANA-style OLAP, that ratio is the bottleneck. Per the CXL Consortium specification, CXL.mem allows the CPU to treat a memory expander module — sitting on a PCIe 5.0 ×8 or ×16 lane group — as another NUMA node, with cache coherence handled by the host root complex.

This is the structural reason hyperscalers are interested in CXL Type 3 in the first place: it disaggregates capacity from channel count. We cover the broader server-memory hierarchy in our LPDDR5 sourcing guide and DDR5 RDIMM 6400 sourcing guide — CXL is the third leg of that 2026 BOM conversation, alongside HBM for accelerators.

CXL Type 1, Type 2, and Type 3 devices — what each one actually is

The CXL spec defines three device profiles distinguished by which sub-protocols they speak (CXL.io, CXL.cache, CXL.mem). The differences are not marketing tiers — they correspond to fundamentally different silicon layouts.

Source: CXL Consortium specifications page, accessed June 2026.

Type 3 is what most engineers mean when they say “CXL memory” — a passive-from-coherence-perspective memory module that hangs off a PCIe slot or EDSFF bay and shows up to the OS as a CPU-less NUMA node. On the OS side, Linux mainline added CXL Type 3 region/DAX support during the 6.x cycle (per the kernel.org CXL driver documentation); Windows Server 2025 documents CXL memory tiering support (per the Microsoft Windows Server 2025 what’s-new documentation). Engineering teams should validate kernel and driver matrix against their target distribution rather than rely on a single version number.

CXL 1.1 vs 2.0 vs 3.0 vs 3.1: the spec timeline that matters for buyers

Most production silicon shipping in 2026 is CXL 2.0. CXL 3.0 silicon exists in pre-production samples; CXL 3.1 is largely a fabric-management refinement that does not affect device-side selection. The wire-speed jump from 32 GT/s to 64 GT/s in CXL 3.0 comes entirely from inheriting the PCIe 6.0 PAM4 PHY — the CXL transaction layer above is largely backward-compatible, which is why memory pooling that worked on a 2.0 switch will continue to work on a 3.0 fabric.

Source: CXL Consortium specifications page and individual vendor product briefs, accessed June 2026.

The 2026 CXL Type 3 silicon landscape: who actually ships

Four vendors carry the conversation today. Naming the actual parts matters because hyperscalers do not say “CXL module” in their RFPs — they say “CZ120-256 in E3.S 2T form factor” or “CMM-D 128GB short-AIC”.

• Micron CZ120. Ships in 128 GB and 256 GB CXL 2.0 memory-expansion module form factors, targeting hyperscaler memory-tiering deployments (source: Micron CZ120 product brief). E3.S 2T form factor.
• Samsung CMM-D. Samsung’s CMM-D CXL 2.0 memory module entered hyperscaler sampling in late 2024 (per the Samsung Semiconductor newsroom CMM-D coverage). Samsung-designed controller; uses Samsung’s own DDR5 dies.
• SK hynix CMM-DDR5. Per industry briefings and the SK hynix newsroom, SK hynix disclosed CMM-DDR5 CXL 2.0 modules in 2024 in 96 GB and 128 GB capacities; volumes are reported as production-allocated to specific OEM customers.
• Astera Labs Leo. The Leo CXL 2.0 Memory Connectivity Platform is positioned as the merchant-silicon bridge between the host CPU and DRAM dies inside a Type 3 module (source: Astera Labs Leo product page). Astera Labs reports design-ins across multiple ODM CXL 2.0 module designs; specific OEM module silicon attributions vary and should be confirmed with the OEM directly.
• Microchip XpressConnect / SmartConnect. Switch silicon for memory pooling fabrics; not an end-module.
• Montage Technology MXC. China-domestic CXL controller; per Montage’s public product roadmap, MXC controllers are positioned for the China-domestic CXL 2.0 supply chain.

If your BOM says “CXL Type 3 module” without a vendor part number, your design is one revision away from being un-quotable. Pick the part, then we can have a sourcing conversation.

CXL Type 3 vs DDR5 RDIMM vs HBM3 in a 2026 server BOM

These three memory tiers do not compete — they stack. Confusing them in a system spec is the most common mistake we see in customer BOMs.

*HBM3/HBM3e bandwidth ranges are derived from JEDEC JESD238A and the Micron HBM3e product brief and SK hynix HBM3e datasheet pages, accessed June 2026.

A 2026 AI-inference rack typically uses all three: HBM on the accelerator for hot tensors, DDR5 RDIMM on the host for active model state, and CXL Type 3 for cold tier and embedding tables.

Decision moment — Engineer. If your workload is bandwidth-bound (training, large-batch inference, FFT-heavy DSP), CXL Type 3 will not save you — its bandwidth-per-dollar is worse than DDR5 and its latency is double. CXL Type 3 only pays off when capacity-per-channel is the constraint and the access pattern tolerates 200+ ns latency. Validate on your real workload before designing CXL slots into the carrier board.

Sourcing reality: why open-market CXL Type 3 modules don’t exist in 2026

Here is the part of the conversation that buyers want and engineers don’t.

Per TrendForce industry briefings (Q1 2026 CXL Memory Module Demand Forecast), CXL Type 3 memory modules are reported to remain hyperscaler-allocated through 2026, with open-market availability limited to evaluation samples and refurbished pulls. Meta and other hyperscalers have publicly discussed CXL Type 3 deployment plans during recent OCP community sessions (per the OCP Global Summit 2025 program archive), with multi-year ramps targeted into 2027 and beyond. Both data points point in the same direction: hyperscaler purchase orders consume the bulk of the wafer commitment from Micron, Samsung, and SK hynix for these modules, and the modules themselves are sold under bilateral supply agreements rather than through traditional distribution.

What that means in practice for 2026:

1. Authorized distribution. Micron, Samsung, and SK hynix CXL modules are not on the public price lists of Arrow, Avnet, or Future Electronics in any volume. A line-card listing usually means “we will quote on allocation request” — not stock.
2. Independent / open market. What surfaces here is overwhelmingly engineering samples, single-unit eval kits leaked from partner programs, or refurbished pulls from decommissioned hyperscaler racks. None of those are appropriate for a production deployment, and the authenticity-risk profile is closer to that of obsolete or EOL semiconductors than to a current-generation DDR5 DIMM.
3. The “I just need one for bring-up” case. This is the realistic ask we can actually help with: a single Micron CZ120 or Astera Labs Leo evaluation module to validate firmware, kernel hot-plug, or NUMA topology on a Granite Rapids board. Cosolvic operates as a Shenzhen-based independent sourcing specialist for these evaluation-sample requests via the secondary channel, with incoming visual and marking inspection, full traceability documentation, and third-party lab decap available on request through partner labs. We carry our standard 100% authenticity or full refund guarantee. We do not claim to hold CXL inventory and we do not pretend that volume orders are realistic in 2026.

Decision moment — Buyer. If procurement is being asked to “secure CXL Type 3 supply” for a 2026 production launch, escalate. The build plan is at risk. Either the project pivots to DDR5-only with deferred CXL adoption in the next refresh, or your firm needs to be at the table with the OEM in a direct allocation negotiation. The open market cannot be the plan.

If your design is genuinely flexible on memory architecture, the lower-risk 2026 path is a diversified sourcing framework built around DDR5 RDIMM with CXL slots routed but un-populated until 2027.

What changed in CXL 3.x that affects design choices today

Three CXL 3.0/3.1 capabilities are worth pencilling onto a 2026 carrier-board design even if you populate it with 2.0 silicon at first power-on. Each is described per the CXL Consortium specification — verify against the current spec revision before committing layout decisions.

• Multi-level switching. Per the CXL Consortium specification, a 3.0 fabric supports switch-to-switch hops, enabling rack-scale memory pools. Routing the CXL lanes through a connector that can be re-cabled to a top-of-rack switch is cheap insurance — particularly if your chassis is on a 3-year refresh cycle and the next refresh lands in 2027 when 3.0 host silicon is broadly available.
• Hardware-coherent memory sharing. Per the CXL Consortium specification, CXL 3.0 supports multiple hosts sharing a region of CXL.mem with hardware coherence; CXL 2.0 only supported pooling (each region pinned to one host at a time). For database fail-over, warm-standby, and shared-state workloads in HPC, this is the more interesting capability. A practical example: a primary/secondary PostgreSQL pair could share a CXL 3.0 region for hot tuple state and eliminate the WAL-shipping latency that defines today’s high-availability ceiling.
• Global Fabric-Attached Memory (GFAM, 3.1). Per the CXL Consortium specification, GFAM scales sharing beyond the rack into a fabric domain. Largely a hyperscaler feature today; relevant to enterprise architects only as a directional indicator of where the spec is heading.

Granite Rapids (Intel Xeon 6) and Turin (AMD EPYC 9005) ship with CXL 2.0 host support — confirm against the Intel Xeon 6 product brief and the AMD EPYC 9005 series product page for the specific SKU’s lane configuration. CXL 3.0 host support is the next-generation Xeon and EPYC silicon, expected through 2027.

FAQ

Q: What is CXL memory expansion in plain English?
A: It lets a CPU treat a DRAM module that lives on a PCIe slot or EDSFF bay as an additional NUMA node, instead of requiring DRAM to sit on the CPU’s own memory channels. This breaks the channel-count cap on capacity and is mainly useful for capacity-bound workloads like in-memory databases, large-embedding inference, and Spark analytics.

Q: What is the difference between CXL Type 1, Type 2, and Type 3 devices?
A: Type 1 is an accelerator with a coherent cache but no attached memory (e.g., a SmartNIC). Type 2 is an accelerator with its own attached memory under host coherence (e.g., a GPU). Type 3 is a memory expander module that presents DRAM or persistent memory to the CPU over CXL.mem and has no compute.

Q: When was CXL 3.0 released and what does it add over CXL 2.0?
A: CXL 3.0 was published in August 2022 (per the CXL Consortium specifications page). It doubles the wire speed to 64 GT/s by adopting the PCIe 6.0 PAM4 physical layer, adds multi-level switching, and introduces hardware-coherent memory sharing across hosts. CXL 2.0 had only single-level switching and host-pinned memory pooling.

Q: Can I purchase CXL Type 3 memory modules in volume in 2026?
A: Realistically, no. Micron CZ120, Samsung CMM-D, and SK hynix CMM-DDR5 modules are reported to be hyperscaler-allocated under direct supply agreements; open-market and authorized distribution stock is essentially limited to evaluation samples through 2026 (per TrendForce Q1 2026 industry briefings). For bring-up, engineering samples are sourceable; for production, plan around CXL or negotiate allocation with the OEM.

Q: Which controller silicon supports CXL 2.0 memory expansion?
A: The merchant-silicon options are Astera Labs Leo (reported to power multiple ODM CXL 2.0 module designs), Microchip XpressConnect for switching, and Montage Technology MXC for the China-domestic supply chain. Samsung and SK hynix use their own internally designed controllers in their first-party modules.

Q: How does CXL Type 3 memory differ from DDR5 RDIMM and HBM3 in a server BOM?
A: HBM3 is on-package with the accelerator at ~1 TB/s but cannot be purchased separately. DDR5 RDIMM sits on CPU memory channels at ~50 GB/s per channel and is broadly available. CXL Type 3 sits on a PCIe lane group at ~32 GB/s per ×8, with 200+ ns latency, used for cold-tier capacity. They stack rather than substitute.

For parts headed into production, who verifies them before they ship matters as much as the part itself. How Cosolvic operates covers our inspection process, counterfeit refund policy, and why we work as an independent distributor rather than a franchise reseller.

Cosolvic role and disclosure

Cosolvic is a Shenzhen-based independent electronic component sourcing specialist. For CXL Type 3, our scope is evaluation-sample sourcing for engineering teams via the secondary channel — single units, bring-up boards, lab validation. We do not represent any CXL module vendor as an authorized distributor and we do not hold CXL inventory. Every sample passes incoming visual and marking inspection with full traceability documentation; third-party lab decap and electrical validation are available on request through partner labs. We carry our standard 100% authenticity or full refund commitment. Volume production sourcing of CXL Type 3 modules in 2026 requires direct engagement with Micron, Samsung, or SK hynix.

Have a CXL evaluation module — Micron CZ120, Samsung CMM-D, an Astera Labs Leo dev board, or a specific OEM ODM unit — that you’re trying to source for engineering bring-up? Send us your BOM at request a quote. We’ll tell you within four hours which lines we have authentic stock for, what’s available within 3-5 days, and which ones genuinely require direct OEM allocation rather than secondary-channel sourcing.

Last updated: 2026-06-11