24LC256 vs AT24C256 vs M24C256 vs CAT24C256: A 2026 I²C EEPROM Cross-Reference and FRAM Upgrade Path

The 256 Kb I²C EEPROM is the universal config-data IC: every embedded BOM has at least one. The 24LC256 (Microchip), AT24C256C (originally Atmel, now Microchip after the 2016 acquisition), M24C256 (STMicroelectronics), CAT24C256 (ON Semiconductor), BR24G256 (ROHM), the FRAM upgrade lane via Fujitsu (RAMXEED) MB85RC256V and Infineon (ex-Cypress) FM24W256, plus Chinese pin-compatibles from Giantec Semiconductor and Holtek, cover the 2026 second-source universe. The 24LC256 AT24C256 EEPROM cross-reference question is one of the most common procurement headaches, and the short answer is: at SOIC-8 and TSSOP-8 the parts substitute well per the JEDEC 24Cxx pinout, but voltage tier, page-write delay, write-cycle endurance, and AEC-Q100 status all vary in ways that bite production firmware if you do not check the datasheet line by line.

An embedded OEM engineer asked us last quarter why his BOM showed AT24C256C-SSHM-T as the original, but the contract manufacturer was sourcing 24LC256-I/SN — and the firmware team had complained the I²C polling loop was “weird” on the new boards. Same SOIC-8 pinout, both running 400 kHz at 3.3 V, both 5 ms max page-write — the substitution worked, but only because the firmware was configured for the slower clock and the supply rail sat where both parts overlap. A swap to a stock 24LC256 in a 1.8 V battery design would have brown-out failed silently. This is the subtlety the cross-reference has to capture.

Why the Nomenclature Is Confusing

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Microchip’s prefix system collapses three product families into the same 24x256 shape:

• 24LC256 — 2.5–5.5 V, 400 kHz I²C (Microchip 24LC256 product page). The original Microchip part; “LC” marks this voltage band.
• 24AA256 — Wide-voltage 1.7–5.5 V, 400 kHz. For low-voltage battery designs where the bus dips below 2.5 V.
• 24FC256 — Fast-mode-plus 1 MHz variant (Microchip 24FC256 product page). Same package and address scheme; differentiated by clock spec.

The Atmel-legacy AT24C series, brought into Microchip’s portfolio after the 2016 acquisition, has its own letter suffixes — AT24C256C, AT24C256D, AT24CS256 — marking process-shrink revisions and feature variants (the “S” suffix adds a hardware serial number block). The AT24C256C datasheet (Microchip DS20006042A) specifies 1.7–5.5 V operation and Fast-Mode-Plus 1 MHz at ≥2.5 V. Microchip continues to sell both 24LC256 and AT24C256C in parallel.

STMicroelectronics’ M24C256 sits on its own. The ST M24C256 product page describes voltage suffix conventions (-W for 2.5 V, -R for 1.8 V), package suffix, and frequency option — the M24C256-F variants quote 1 MHz operation and the family datasheet specifies more than 4 million write cycles, distinctly higher than the 1 million typical for Microchip and ROHM parts. ON Semi’s CAT24C256 is the legacy Catalyst Semiconductor line absorbed in 2008; functionally aligned with JEDEC 24Cxx, with AEC-Q100 status verified per ordering suffix.

This is the genuine 24LC256 AT24C256 EEPROM cross-reference confusion: same 256 density across five Western vendors and several Chinese pin-compatibles, six voltage tiers, two clock speeds, and a write-protect convention consistent at SOIC-8 but not at WLCSP or SOT23-5.

Hard Pin-Compatibility Rules

For SOIC-8 (the dominant production package), the JEDEC 24Cxx convention is well established: pins 1-3 are address-select inputs A0/A1/A2, pin 4 V_SS, pin 5 SDA, pin 6 SCL, pin 7 the write-protect WP, pin 8 V_CC. This pinout holds across Microchip 24LC256/24AA256/24FC256, AT24C256C, ST M24C256, ON Semi CAT24C256, ROHM BR24G256, Giantec GT24C256, and Holtek HT24LC256 in their standard 8-lead SOIC packages. TSSOP-8 inherits the same pin order; DIP-8 is the through-hole equivalent.

WLCSP and SOT23-5 are different. Pin pitch and pinout are vendor-specific, the WP pin is sometimes absent on 5-pin variants, and substitution requires layout redesign. Verify the package-specific datasheet pinout on the exact ordering code before treating any small-form-factor 24Cxx as a drop-in.

The 2026 Cross-Reference Matrix

This is the production-grade 24LC256 AT24C256 EEPROM cross-reference for SOIC-8 substitution decisions in 2026. Numbers are drawn from each vendor’s most recent public datasheet revision available as of June 2026; verify against the live datasheet for any production qualification, and confirm AEC-Q100 status against the exact ordering suffix.

The voltage range, clock, and page-write fields above reflect the typical industrial-suffix variant most commonly designed-in on small-batch industrial and IoT BOMs. Wider-temperature automotive variants exist for several of these parts under different suffix codes — verify AEC-Q100 status against the exact ordering code, not the family name.

When Pin-Compatibility Actually Works

A drop-in substitution at SOIC-8 is safe when four conditions all hold: (1) package matches exactly; (2) the voltage tier of the replacement is equal to or wider than the design’s V_CC range; (3) the maximum I²C clock spec meets or exceeds the firmware’s clock setting; (4) the page-write delay is equal to or shorter than the firmware’s polling timeout, OR the firmware uses ACK-polling rather than fixed delay.

In practice, a 24LC256-I/SN substitutes for an AT24C256C in a 3.3 V board at 400 kHz with no firmware change. A 24LC256 cannot substitute for a 24AA256 in a 1.8 V battery design — the 24LC256’s 2.5 V minimum brown-outs below the rail. A CAT24C256WI substitutes for a BR24G256FVT-3A cleanly at 1 MHz industrial. For migration playbook context when a part hits NRND status, see our NRND decision framework.

When Pin-Compatibility Does NOT Work

Page-write delay drift. Firmware that uses a fixed delay (rather than ACK-polling) can overrun the bus on a slower-write part. ACK-polling is the correct pattern; fixed delay breaks during second-source qualification.

Endurance variance per vendor datasheet. Microchip 24LC256, Holtek HT24LC256, ROHM BR24G256-3A, and Giantec GT24C256C standard each specify 1 million erase/write cycles per their public datasheets; ST M24C256 specifies more than 4 million per the ST product page; Giantec GT24C256B automotive is rated for 4 million per Giantec’s automotive datasheet. For high-write-rate workloads (event logging, counter persistence, calibration tables updated per power cycle), 1 M versus 4 M cycles is the difference between a 5-year and a 20-year field-service life. These are vendor-specific guaranteed values.

AEC-Q100 status drift. The wrong suffix breaks IATF 16949 customer audits. Holtek HT24LC256 is not AEC-Q100 qualified per its public datasheet. ROHM BR24G256-3A industrial is not AEC-Q100 — automotive applications require a separate ROHM ordering suffix. Giantec GT24C256C standard is not AEC-Q100; GT24C256B is qualified Grade 2 per Giantec’s automotive datasheet. Verify the exact ordering code, do not generalize across the family.

The FRAM Upgrade Path

Ferroelectric RAM (FRAM) is the clean upgrade lane when EEPROM endurance or write-speed becomes a design constraint. The two production-grade 256 Kb I²C FRAM parts in the standard JEDEC 24Cxx pinout are the Fujitsu / RAMXEED MB85RC256V and the Infineon (ex-Cypress) FM24W256, both in pin-compatible SOIC-8.

No page-write delay. A FRAM byte write completes within the I²C transaction itself; no internal program cycle, no ACK-polling. This eliminates the firmware timeout class of bugs entirely.

Endurance several orders of magnitude higher. Fujitsu MB85RC256V specifies 10¹² read/write cycles per byte per its datasheet; the Infineon FM24W256 specifies 10¹⁴ cycles per the Cypress/Infineon datasheet. EEPROM is typically 10⁶. For energy-buffered shutdown logging, high-frequency calibration updates, or safety-critical event recorders, FRAM removes endurance from the design’s risk register. Neither standard part is AEC-Q100 qualified — the Fujitsu/RAMXEED MB85RC256TY automotive variant is the AEC-Q100 Grade 2 path for vehicle BOMs.

Cost premium. Production unit pricing for 256 Kb FRAM is directionally 5-10× the equivalent EEPROM as observed in 2026 distributor pricing — verify per quote, since the actual ratio fluctuates with FRAM allocation cycles, fab capacity, and the specific suffix being compared. Justified when the design genuinely needs the endurance or no-delay write semantics; over-engineering for boot-time configuration data.

For broader NV-memory supply context, see our NOR Flash 2026 supply analysis.

Counterfeit Detection on EEPROM Lots

Serial EEPROM is a counterfeit-prone class — small package, low value-per-unit, date-code consistency hard to verify visually. Cosolvic’s standard diligence on broker lots includes date-code uniformity inspection, reel-end audit, and visual inspection against the manufacturer’s package photo and laser-mark conventions. For production-critical lots — automotive design-ins, medical-device BOMs, or any lot where the customer’s quality system requires it — we can arrange decap visual inspection plus electrical functional test on a sample as a per-quote, per-lot service decided up front, not a default line-item. Our broader component authentication procedures cover the full inspection chain.

Cosolvic’s Role on the EEPROM BOM Line

Broker NOS for Microchip / ST / ON Semi / ROHM originals. When a buyer needs an exact-suffix match for an existing AVL — say, AT24C256C-SSHM-T for an industrial gateway already in production — Cosolvic sources through the Shenzhen broker network with date-code matching and authenticity verification. Lead time 3-5 days typical, subject to broker stock check. We are an independent distributor, not authorized for any of these brands.

Samples for Giantec / Holtek Chinese pin-compatible alternatives. When a design team is open to a Chinese pin-compatible alternative for cost-down or supply-chain decoupling, we supply sample quantities for fit-and-function testing. Production quantities follow the buyer’s qualification timeline.

FRAM via authorized channels with supplemental service. FRAM is allocation-controlled and best procured through the manufacturer’s authorized chain. Cosolvic acts as a supplemental layer — small lots, expedited delivery, or pairing FRAM with the surrounding BOM lines we are already sourcing — rather than the primary supply path.

For taxonomy on when each lane applies, see our obsolete and EOL classification guide.

For parts headed into production, who verifies them before they ship matters as much as the part itself. How Cosolvic operates covers our inspection process, counterfeit refund policy, and why we work as an independent distributor rather than a franchise reseller.

FAQ

Is AT24C256 the same as 24LC256?

Not the same silicon, but they substitute well in most production designs. Both are 256 Kb I²C EEPROM in SOIC-8 with the JEDEC 24Cxx pinout. The AT24C256C (Microchip-owned post-2016) supports 1 MHz at ≥2.5 V and 1.7-5.5 V wide voltage; the 24LC256 is 400 kHz and 2.5-5.5 V. If your design runs 400 kHz at 3.3 V or 5 V, either works. At 1.8 V or 1 MHz, the 24LC256 is not a drop-in — use the AT24C256C, 24AA256, or 24FC256.

Can I drop in a Chinese 24C256 without firmware change?

Sometimes yes, sometimes no. A Giantec GT24C256 or Holtek HT24LC256 in SOIC-8 follows the same pinout and operates at a comparable nominal voltage range (HT24LC256 is 2.2-5.5 V; GT24C256C is 1.7-5.5 V). The firmware risk is page-write timing mismatch: if your firmware uses a fixed delay rather than ACK-polling, a part with a longer worst-case write cycle can silently corrupt data. Test on bench hardware under worst-case write workload before committing to a full production lot.

When should I use FRAM instead of EEPROM?

Three scenarios justify FRAM’s directional 5-10× cost premium: high write-rate workloads where EEPROM’s 1 M (or 4 M) endurance becomes a wear-out concern; energy-buffered shutdown logging that cannot afford the page-write delay; and safety-critical event recorders. For boot-time configuration data, EEPROM is the right answer and FRAM is over-engineering.

Are all 24C256 parts AEC-Q100 qualified?

No — AEC-Q100 status is per part and per ordering suffix, not per family. Each public datasheet must be checked individually. Holtek HT24LC256 is not AEC-Q100. ROHM BR24G256-3A industrial is not AEC-Q100. Giantec GT24C256B is AEC-Q100 Grade 2 while GT24C256C standard is not. Verify the exact ordering code against the manufacturer’s qualification documentation.

How does Cosolvic handle counterfeit risk on EEPROM lots?

Standard diligence on every broker lot includes date-code uniformity inspection, reel-end audit, and visual mark verification against the manufacturer’s package photo. For production-critical lots, decap visual inspection plus electrical functional test on a sample is available as a per-quote, per-lot service decided up front, not a default line-item. Lots that fail authenticity inspection are returnable under our 100% refund-for-authenticity-issue policy.

Does Cosolvic supply FRAM (MB85RC256V, FM24W256)?

FRAM is allocation-controlled and best procured through the manufacturer’s authorized channel. Cosolvic acts as a supplemental service layer for FRAM: small lots, expedited fulfillment, pairing FRAM with the surrounding BOM lines we are sourcing through the broker network. We do not position ourselves as a primary FRAM supply path.

Last updated: 2026-06-25

Working a 256 Kb I²C EEPROM line and need a second source? Send the BOM line plus your firmware’s I²C clock, write-cycle pattern, voltage rail, and AEC-Q100 requirements at request a quote. We will return a per-suffix availability view across Microchip, STMicro, ON Semi, ROHM, Giantec, and Holtek within four hours, and flag any cases where the substitution carries a firmware-side risk worth verifying on bench hardware before lot commitment.